The present invention generally relates to a protection of an electronic circuit against electrostatic discharges (ESD), and especially relates to a protection device for mixed voltage circuits.
In applications like hard-disk drive read channel units that require maximum speed of an analog processing chain it is advantageous to make use of the fast devices that are available in CMOS technology. These devices are operated in the digital domain and are formed with thin oxides. The operating conditions are limited to specified maximum voltages, especially with respect to the gate-source connection, the gate-drain connection and the drain-source connection.
Thus the supply voltage for thin oxide circuit units is low such that deep sub-micron processes can be applied. Analog front end circuits operating at extreme low supply voltages suffer from the loss of headroom available for biasing these devices. Due to this fact and due to the low drain-source impedance of the core devices the required transistor dimensions increase to allow a biasing of e.g. a current source at a low drain-source voltage operating point. With the increase of transistor size parasitic capacitances also increase which results in parasitic poles that can dominate the signal path. Therefore it is necessary to use higher supply voltages in the signal path in order to obtain an optimum headroom of the devices resulting in smaller device sizes. An appropriate biasing of the thin-oxide circuit units (core devices) ensures that these devices are not damaged. This results in a so-called mixed-voltage circuit unit.